Processes for forming transistors include creating split-trench transistors, wherein the gate structure inside the trench is split into two segments. Trench-based transistors include field-effect transistors (FETs) such as power MOSFETs. Transistors formed using trenches may include gate electrodes that are buried in a trench etched in the silicon. This may result in a vertical channel. In many such FETs, the current may flow from front side of the semiconductor die to the back side of the semiconductor die. Transistors formed using trenches may be considered vertical transistors, as opposed to lateral devices.
Trench FET devices may allow better density through use of the trench feature. However, trench FET devices may suffer from packaging issues when used in modules and devices. Furthermore, a thin back grind is typically required to use such trench devices.
FIG. 1 illustrates a known integrated circuit (IC) structure 10 including a number of trench-based semiconductor device, more specifically, trench FETs. The example IC structure 10 includes a highly-doped bulk silicon substrate 12, a lightly-doped epitaxy (EPI) layer 14 formed over bulk substrate 12, and a transition region 16 between EPI layer 14 and bulk substrate 12. Transition region may define a transition from the more lightly doped EPI layer 14 to the more heavily doped bulk substrate region 12. The more lightly doped region may be light enough to survive a breakdown field. The resistance of this region may have consequences for operation of the FET because this area is typically not a pure metal.
Doped source regions 20 may be formed in a top portion of EPI layer 14, and poly gates 30 may be deposited in trenches formed in EPI layer 14. An oxide or insulation layer 26 may be formed over the EPI layer 14, and source contacts 22 and gate contacts (not shown) may be formed on the top or front-side of the wafer to connect the source regions 20 and poly gates 30 to conductive elements at the top or front-side of the wafer, e.g., an overlying metal layer 24 connected to source contacts 22 and/or front-side gate contacts (not shown). Drain contacts may be located on the bottom or back-side of the wafer, as indicated in FIG. 1, to define a number of vertical trench FETs. This type of vertical FET may offer better density when compared with lateral FETs. A thin back grind may be used to reduce parasitic resistance.
FIG. 2 illustrates the performance of the epitaxy region 14, transition region 16, and bulk substrate 12 in terms of carrier concentration versus depth. The left, flat portion of the curve represents electrical performance in the EPI 16, the rising part of the curve represents electrical performance in the transition region 14, and the right, flat portion of the curve represents electrical performance in the bulk region 12. In some structures, the bulk region 12 may be 50 to 150 microns thick, and the transition 16 may approximately one micron thick. For a typical 25 volt FET, the die area might be about 7 mm2, and generate a total of 0.5 mohm, including resistance of 0.29 mohm for the back grind and 0.2 mohm for the transition.